(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method for using the same process steps to form both a capacitor plate structure, and a metal contact structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve semiconductor device performance, while still attempting to reduce the cost of these same semiconductor devices. Micro-miniaturization, or the ability to create semiconductor devices with sub-micron features, have allowed the performance and cost objectives to be realized. Semiconductor devices, such as DRAM devices, fabricated with sub-micron features, experience performance enhancements, as a result of reduced performance degrading capacitances and resistances, in turn realized from the use of smaller features. In addition the use of sub-micron features result in the attainment of smaller chips, thus allowing more chips to be obtained from a specific size starting substrate, thus reducing the processing cost for a specific DRAM chip.
In addition to the cost reductions, realized via micro-miniaturization, further decreases in DRAM costs can be realized by process simplification. For example the ability to use only one process sequence, to form structures that were previously processed independently, requiring additional process sequences, result in costly reductions for DRAM devices. This invention will describe a process, (SMP), for Simultaneously forming a capacitor Plate and a Metal contact, using the same process sequence. Prior art, such as Lou, et al, in U.S. Pat. No. 5,597,754, describe a DRAM device with a stacked capacitor, (STC), structure, with a polysilicon capacitor plate, and a metal contact structure, however that prior art does not combine the formation of the capacitor plate and the metal contact structure, in a single process sequence, as this invention will describe.